A guide to Metastability

One of the major concerns in designing of a digital sequential circuit is the problem of metastability. In this post, we will have look at it.

If the output of the flip-flop is neither in the HIGH state nor in the LOW state but it lies somewhere between them, then this state is known as the Metastable state (quasi-stable state). The output will eventually settle to HIGH/LOW state but the time that it takes to reach one of these stable states and the state it reaches(HIGH/LOW) remains unpredictable. This whole process of a flip-flop going into Metastable state and then settling into one of the stable states(HIGH/LOW) is known as Metastability.

To understand it better, let's take an analogy. Consider a ball at position 1 in front of a hill as in figure 1. If you hit the ball too lightly, it will in position 1 only. If you hit it too hard, the ball will reach position 2. Can you make the ball stop and stay at the top of the hill? It is metastable because even if you were able to land the ball at the top, even the slightest disturbance like wind will make it fall. And the position it will fall to can't be said for sure. The positions 1 and 2 can be compared to HIGH and LOW states of a flip-flop and the metastable state with the top of hill.

Figure 1: Analogy for metastability

Causes:

Here we discuss some of the possible causes for metastability in a system:

• The input to a flip-flop changes between the setup and hold time around the clock edge. 
• The input to a flip-flop is asynchronous.
• Setup time constraint(STC) or hold time constraint(HTC) is not met for the system.
• When we try to connect two systems operating at different frequencies or at same frequencies but different phase.

If you look carefully at the above points, we notice that the remaining points are derived from the first point itself, i.e. the input being asynchronous, STC/HTC being not met all these statements basically mean that the input to a flip-flop changes between the setup and hold time.  

Effects:

Once a flip-flop goes into a metastable state, the amount of time it may take to settle to one of the valid states remains unknown. So, if the data output signal resolves to a valid state before the next register captures the data, then the metastable signal does not negatively impact the system operation. But if the metastable signal does not resolve to a valid state before it reaches the next register, it can cause the system to fail and these failures are very difficult to track down and correct.

So, care must be taken while designing a system for possible metastabilities. We can't eliminate metastability completely, but synchronizers are used to reduce the chances of failure and is discussed in next section.

Synchronizers:

Synchronizer can be thought of as an interface connecting the outer asynchronous world to the synchronous system and tries to eliminate metastability as much as possible. It utilizes the fact that for a flip-flop in the metastable state the probability that it will settle to a valid state increases exponentially with time.

A synchronizer can be built simply using a sequence of registers as in figure 2. These registers allow additional time for a potentially metastable signal to resolve to a known value before the signal is used in the rest of the design.

Figure 2: A synchronizer

The time available in the synchronizer register-to-register paths is the time available for a metastable signal to settle and is known as the available metastability settling time(t_set). For example, in figure 2, if the output of FF1 is in the metastable state then it must settle to a valid state atleast setup time before next clock edge else the synchronizer fails. Therefore, t_set can be calculated as T_CLK - t_setup. 

MTBF:

The mean time between failures (MTBF) due to metastability provides an estimate of the average time between instances when metastability could cause a design failure. Higher the MTBF, better the design in handling metastability.  The required MTBF depends on the system application. For example, a life-critical medical device requires a higher MTBF than a consumer video-display device.

MTBF for a synchronizer device can be calculated using the formula:

t_set is the available metastability settling time,
C1 and C2 are device dependent constants,
f_CLK is the clock frequency,
f_DATA is the toggling frequency of the asynchronous input data signal

This completes our discussion on metastability. Hope you find it useful!

Syllabus to prepare for Hardware Profile

If you are preparing for a job process for on-campus placements or as a fresher in Electronics domain, this post will guide you through the topics you should cover and some resources from where it can be done. If you aiming to be a part of companies like Qualcomm, NXP, ST Microelectronics, Texas Instruments, Nvidia, Intel, Synopsys, Mentor Graphics and many other for hardware profile, they expect you to have a deep understanding of the following topics. 

The selection process for these companies usually consists of three rounds(on-campus placements). First round is a test, online/offline depending on the company. This test consists of questions related to general Aptitude and Core Subjects. After that technical interviews are there. Mostly more than one technical interviews are there. Finally, HR round. The topics mentioned below will cover your first two rounds. 

1. Basic R, L, C (Network theory):
Usually, intuition based questions are asked on this topic during interviews. There is no specific content that I can suggest for this topic, but I personally found the below course by Anant Aggarwal very helpful.
-- edX course: Circuits and electronics 1,2 and 3  

2. MOSFETs:
Working of MOSFETs, its current-voltage characteristics, small signal, large signal, etc. You should be thorough with this device because of a majority of the electronics companies at present work on MOSFETs only, so they expect from you that you know this topic in detail.
-- Microelectronics by Adel S.Sedra and Kenneth C.Smith, Fifth edition - chapter 4
  
3. Diodes, BJTs:
-- Microelectronics by Adel S.Sedra and Kenneth C.Smith, Fifth edition - chapter 3 and 5

4. Basic Digital:
Boolean algebra, codes, logic gates, k-map, Combinational logic, sequential logic, registers, counters, logic families. 
-- Digital Design by Morris Mano
-- Fundamentals of Digital Circuits by Anand Kumar (This book has lots of questions to practice)

5. FSM:
This is one of the most important topics for an interview in digital profile. You should be capable of solving a question using both Mealy and Moore machines. 
-- Fundamentals of Digital Circuits by Anand Kumar (practice as many questions as possible)
-- Digital Design and Computer Architecture by David Money Harris and Sarah L. Harris

6. CMOS :
CMOS based Inverter design (static and dynamic operation), pass transistors, CMOS based NAND, NOR and general logic design.
-- Microelectronics by Adel S.Sedra and Kenneth C.Smith, Fifth edition - chapter 10 (Have a detailed understanding of each and every concept of this chapter) 

7. Microprocessors:
-- 8085 Microprocessor by Ramesh S Gaonkar

8. Computer Architecture:
Memory Organization(RAM, cache memory, Virtual memory) in a system should also be covered
-- Computer System Architecture by Morris Mano
-- Digital Design and Computer Architecture by David Money Harris and Sarah L. Harris (reads memories from this)

9. Op-amps, Filters: 
-- edX course: Circuits and electronics 3 
-- Microelectronics by Adel S.Sedra and Kenneth C.Smith, Fifth edition - chapter 3 and 5

10. Static Timing Analysis (STA):
You can refer to my video lectures on this topic that will guide you through the complete basics and few of the most commonly asked interview questions related to STA. 
-- ElectroTuts Playlist on STA
 -- or you can refer to the vlsi-expert blog

11. VHDL/Verilog:

You must be familiar with coding in one of these two popular hardware description languages. I would say that you should learn the same language your college follows in its curriculum as it will be easier for you to follow. You can refer to books from your course or just read from google.

Apart from these topics knowledge of bode plot, basics of control engineering may also be helpful. Aptitude must also be prepared to clear the first round and you can expect some puzzles also during the technical interviews.

I would personally recommend you to read "Digital Design and Computer Architecture by David Money Harris and Sarah L. Harris" as it helped me a lot during my interviews. 

I hope you find this post useful! Best of luck with your interviews!

FIFO size/depth Calculation

Assume that you have two systems T and R which operate at frequencies 200MHz and 20MHz respectively. How can you send data from A to B without any loss?

Fig: Question related to FIFO 

In this post, we will try to get an answer to these type of questions where we need to communicate from a high-frequency system (T) to a low-frequency system (R). If the system T sends some B bits of data at a time, then the system R will receive some bits of data and due to its slow speed it will not be able to cope up with the transmitting speed of T, hence the data will be lost. That data which has a possibility of getting lost, must be stored for some time until the slow system R reads it. This storage of data between T and R can be done using a FIFO buffer.

FIFO Introduction:

FIFO stands for first in first out. As the name suggests, it is a type of buffer which stores a given number of bits and the output from the buffer is taken in the same order as the input is stored. It can be developed using a simple serial in serial out shift register, where the number of flip-flops in the register is equal to the number of bits we need to store in this register.

FIFO Size/Depth Calculation:

Fig: Solution to the above question

Coming back to our question, we saw that a FIFO can be introduced between T and R to prevent data loss. Now, How many bits should our FIFO be capable of storing? This quantity also known as FIFO size/ FIFO depth is calculated considering the worst case scenario.

We get the worst scenario when the system T writes data at the maximum possible rate and system R reads data from the buffer at the minimum rate.

Let the maximum amount of data that the transmitter can write at a time be B bits. This is also known as the burst size.

Let the rate at which system T transmits data (writes into FIFO buffer) = R_T Hz.
similarly, let the rate at which system R receives data (reads from FIFO buffer) = R_R Hz.

As we have a burst size of B, the time taken to write B bits of data = B/RT seconds.
The number of bits system R can send in the same time = (B/R_T)* R_R bits.

The remaining bits must be stored in the buffer so that we don't lose it which gives us the depth of buffer.
Therefore, Depth = B - (B/R_T)*R_R  bits.

Note that we have not considered the idle cycles for read and write operation. If specified in the question, we can incorporate those also by analyzing the question in a similar manner as we saw above.

Thanks for reading!