Astable Mode of 555 Timer IC is discussed in this post. This is the part 2 of the series on 555 Timer IC. Part 1 discusses the pin configuration and working of the internal circuit of 555 Timer IC, so might want to have a look at it, if you haven’t read it already: 555 Timer IC - Introduction.
Introduction to Astable Mode:
555 IC oscillates continuously between HIGH and LOW, generating pulses of a particular frequency at the output, in its astable mode. The frequency, at which the 555 oscillates, is controlled by adjusting the values of resistors and capacitor used to implement the circuit. This is the most popular mode of operation of 555 Timer. This mode can be used to generate clock signals, also the output frequency when connected to a speaker can produce sound.
Circuit Diagram:
The circuit diagram below shows the connection of 555 in astable mode. How does this circuit work? How to decide on the value of resistors (RA and RB) and capacitor (C)? What is the Time period of the pulse generated at the output? What is its Duty cycle? All these questions will be answered in this post.
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| Fig 1: (a) 555 connected in Astable Mode, (b) Output voltage at pin 3 of the 555. |
Working:
Assume that the capacitor ‘C’ is completely discharged initially. Therefore, the voltage at pin 2 and 6 or node ‘VC’ is 0 at time t=0. Since, VC = 0, this is same as case 2 from the previous post. So, the output of comparator 1 is ‘0’, comparator 2 is ‘1’. The output of 555 (VO) is ‘1’ and the Q1 transistor is cut-off. So, the capacitor C starts to charge through RA and RB to VCC.
Once the voltage VC crosses 2*VCC/3, the output of comparator 1 goes ‘1’, comparator 2 switches to ‘0’, hence the output switches to ‘0’ and Q1 is in saturation as in case 1 of the previous post. Now, as Q1 is in saturation, pin 7 can be assumed to be connected to ground, thus the capacitor C which is charged to 2*VCC/3 begins to discharge through the resistor RB.
As VC decreases and falls below VCC/3, 555 IC switches itself again to the state it was initially in and the process repeats itself. This cycle of charging and discharging of the capacitor keeps on repeating itself until the power supply is disconnected, thus causing the output of 555 Timer IC to oscillate. Since we have seen the working of this circuit, next we discuss how to find time period the pulse generated.
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| Graph of the Vc vs time and corresponding Vo vs time for the circuit shown in Fig 1. |
Time Period:
If you notice in the graph of VO, the HIGH time of the first cycle (TH1) is greater than the HIGH time of remaining pulses (TH). This is known as first cycle timing error. We can ignore this error most of the times because we can use the 555 from its second cycle.
To find the HIGH time (TH) of the pulse, we look at the corresponding curve of VC. C is charging through RA and RB from VCC/3 to VCC. Therefore, the time constant of charging becomes C*(RA + RB) and for charging the equation of VC(t) becomes as the first equation in the following figure. Capacitor charges to 2*VCC/3 after TH time has passed. Put this in the equation to get the second equation and hence HIGH time.
Similarly, to find the LOW time (TL) of the pulse, we look at the corresponding curve of VC. C is discharging through RB from 2*VCC/3 to ground. Therefore, the time constant of discharging becomes C*RB and for discharging the equation of VC(t) becomes as the first equation in the following figure. The capacitor discharges to VCC/3 after TL time has passed. Put this in the equation to get the second equation and hence LOW time.
555 oscillates continuously between HIGH and LOW in astable mode. So, the time period (T) of a single pulse is given by the sum of HIGH and LOW time.
T = TH + TL = C.(RA + 2.RB).ln2.
From this equation, if we know the values of resistors and capacitor, we can find the time period and hence the frequency of oscillations (f = 1/T). or if we want to fix our frequency, we can choose the values of resistors and capacitor correspondingly.
Duty Cycle:
Since we get rectangular pulses at the output, it is useful to know the duty cycle of the pulse. Duty cycle is defined as the time for which a pulse remains HIGH in its time period. Therefore we get,
Notice from the equation of duty cycle, that this circuit can never produce a square pulse, i.e. 50% duty cycle.
This completes our analysis of 555 Timer IC in Astable mode. I will cover 555’s Monostable mode in my next tutorial. I hope you find this tutorial useful. Comment your opinions and topics you want me to discuss in future.
Thanks for reading!
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