A guide to Metastability

One of the major concerns in designing of a digital sequential circuit is the problem of metastability. In this post, we will have look at it.

If the output of the flip-flop is neither in the HIGH state nor in the LOW state but it lies somewhere between them, then this state is known as the Metastable state (quasi-stable state). The output will eventually settle to HIGH/LOW state but the time that it takes to reach one of these stable states and the state it reaches(HIGH/LOW) remains unpredictable. This whole process of a flip-flop going into Metastable state and then settling into one of the stable states(HIGH/LOW) is known as Metastability.

To understand it better, let's take an analogy. Consider a ball at position 1 in front of a hill as in figure 1. If you hit the ball too lightly, it will in position 1 only. If you hit it too hard, the ball will reach position 2. Can you make the ball stop and stay at the top of the hill? It is metastable because even if you were able to land the ball at the top, even the slightest disturbance like wind will make it fall. And the position it will fall to can't be said for sure. The positions 1 and 2 can be compared to HIGH and LOW states of a flip-flop and the metastable state with the top of hill.

Figure 1: Analogy for metastability

Causes:

Here we discuss some of the possible causes for metastability in a system:

• The input to a flip-flop changes between the setup and hold time around the clock edge. 
• The input to a flip-flop is asynchronous.
• Setup time constraint(STC) or hold time constraint(HTC) is not met for the system.
• When we try to connect two systems operating at different frequencies or at same frequencies but different phase.

If you look carefully at the above points, we notice that the remaining points are derived from the first point itself, i.e. the input being asynchronous, STC/HTC being not met all these statements basically mean that the input to a flip-flop changes between the setup and hold time.  

Effects:

Once a flip-flop goes into a metastable state, the amount of time it may take to settle to one of the valid states remains unknown. So, if the data output signal resolves to a valid state before the next register captures the data, then the metastable signal does not negatively impact the system operation. But if the metastable signal does not resolve to a valid state before it reaches the next register, it can cause the system to fail and these failures are very difficult to track down and correct.

So, care must be taken while designing a system for possible metastabilities. We can't eliminate metastability completely, but synchronizers are used to reduce the chances of failure and is discussed in next section.

Synchronizers:

Synchronizer can be thought of as an interface connecting the outer asynchronous world to the synchronous system and tries to eliminate metastability as much as possible. It utilizes the fact that for a flip-flop in the metastable state the probability that it will settle to a valid state increases exponentially with time.

A synchronizer can be built simply using a sequence of registers as in figure 2. These registers allow additional time for a potentially metastable signal to resolve to a known value before the signal is used in the rest of the design.

Figure 2: A synchronizer

The time available in the synchronizer register-to-register paths is the time available for a metastable signal to settle and is known as the available metastability settling time(t_set). For example, in figure 2, if the output of FF1 is in the metastable state then it must settle to a valid state atleast setup time before next clock edge else the synchronizer fails. Therefore, t_set can be calculated as T_CLK - t_setup. 

MTBF:

The mean time between failures (MTBF) due to metastability provides an estimate of the average time between instances when metastability could cause a design failure. Higher the MTBF, better the design in handling metastability.  The required MTBF depends on the system application. For example, a life-critical medical device requires a higher MTBF than a consumer video-display device.

MTBF for a synchronizer device can be calculated using the formula:

t_set is the available metastability settling time,
C1 and C2 are device dependent constants,
f_CLK is the clock frequency,
f_DATA is the toggling frequency of the asynchronous input data signal

This completes our discussion on metastability. Hope you find it useful!